Reconfigurable data processing arrays are known in the art. Reference is being made to the previous applications and/or publications of the present applicant/assignee all of which are incorporated herein by way of reference. Accordingly, the devices described hereinafter may be multidimensional (n>1) arrays comprising coarse grained computing and/or data operation elements allowing for runtime reconfiguration of the entire array or parts thereof, preferably in response to a signal indicating reconfigurability to a loading unit (CT, CM or the like).
Now, several of these data processing arrays have been built (i.e. Xpp1, XPP128, XPP2, XPP64). It is however desirable to improve the known device further as well as to improve methods of its operation.